# Build Reliable ARM Cortex-M Firmware

ARM Cortex-M firmware can fail because of interrupt races, cache incoherence, and incorrect peripheral access. This skill provides platform-specific design, implementation, and validation guidance.

## Install

```bash
npx skillstore add sickn33/arm-cortex-expert
```

## Metadata

- Status: approved
- Slug: sickn33-arm-cortex-expert
- Skillstore revision: r2
- Version status: missing
- Tree hash: 732be4974e1e850d79a6d2b1cfdb02ca9c31a9513e2d38831963bb821f06ae9d
- Author: sickn33
- GitHub username: sickn33
- License: MIT
- Repository: https://github.com/sickn33/antigravity-awesome-skills/tree/main/skills/arm-cortex-expert
- Ref: 86d877f219e2131f05dd5b37c5e329c71c7b8ec4
- Supported tools: Claude, Codex, Claude Code
- Audit status: complete
- Agent install advisory: allowed
- Manual install advisory: allowed
- Artifact signature: available
- Audit attestation: unavailable
- Human verification: not\_verified
- Risk factors: scripts, external\_commands
- Quality score: 78
- Quality tier: bronze
- Public page: https://skillstore.pages.dev/skills/sickn33-arm-cortex-expert
- Manifest: https://skillstore.pages.dev/api/skills/sickn33-arm-cortex-expert/manifest

## Capabilities

- Designs peripheral drivers for I2C, SPI, UART, ADC, DAC, PWM, USB, CAN, and SDIO.
- Explains interrupt priorities, critical sections, atomic access, ring buffers, and nonblocking data paths.
- Guides DMA buffer alignment, cache maintenance, memory placement, and Cortex-M7 memory barriers.
- Compares Teensy 4.x, STM32, nRF52, and SAMD platform APIs and constraints.
- Diagnoses HardFaults, stack overflows, invalid MMIO access, and timing problems from supplied evidence.
- Proposes C, C\+\+, or Rust firmware structures with validation steps and documented tradeoffs.

## Use Cases

- Develop a Peripheral Driver: Create a nonblocking driver design with initialization, transactions, interrupt handling, error recovery, and target validation.
- Review Real-Time Behavior: Assess interrupt priorities, critical sections, DMA coherency, memory barriers, and latency risks before integration.
- Diagnose Target Faults: Interpret fault registers, stack frames, memory access failures, and platform constraints to plan focused experiments.

## Prompt Templates

### Explain Interrupt Priorities

```
Explain the Cortex-M interrupt priority model for [MCU] and recommend priorities for [peripherals]. Include assumptions, tradeoffs, and verification steps.
```

### Design an SPI Driver

```
Design a nonblocking SPI sensor driver for [board] using [framework]. Cover initialization, transactions, error handling, interrupts, and a target test plan.
```

### Review DMA Safety

```
Review this [language] DMA implementation for [MCU]. Identify alignment, cache coherency, synchronization, memory barrier, and lifetime defects, then propose corrected architecture.
```

### Analyze a HardFault

```
Analyze the supplied HardFault registers and stack frame for [MCU]. Rank likely causes, map evidence to each cause, and define confirming experiments.
```

## Limitations

- Cannot verify generated firmware on physical hardware or measure electrical timing.
- Requires the exact MCU, board, clock tree, peripheral pins, and toolchain for reliable implementation details.
- The referenced implementation playbook is not included in this skill package.
- Generated code still needs datasheet review, compilation, static analysis, and target testing.

## Best Practices

- Provide the exact MCU, board revision, framework, compiler, clock configuration, and peripheral requirements.
- Check generated advice against the reference manual, datasheet, errata, and platform library version.
- Validate on target hardware with fault injection, timing measurements, boundary cases, and recovery tests.

## Anti Patterns

- Do not apply Cortex-M7 cache guidance to devices without caches or identical memory architecture.
- Do not copy register addresses, interrupt priorities, or DMA mappings between MCU families.
- Do not accept generated firmware without compilation, static analysis, hardware tests, and electrical constraint review.

## Security Audit

- Audited at: 2026-07-23T20:17:03.702\+00:00
- Summary: All 34 static alerts are false positives caused by Markdown backticks, code fences, a Rust API named with, and legitimate firmware diagnostics. The skill contains no executable scripts, command execution, reconnaissance intent, prompt injection, or data-exfiltration behavior.

## Stats

- Views: 114
- Downloads: 17
- Favorites: 0
- Popularity score: 0