Skills arm-cortex-expert
📦
arm-cortex-expert
Content revision r2 Safe ⚡ Contains scripts⚙️ External commands
Build Reliable ARM Cortex-M Firmware
ARM Cortex-M firmware can fail because of interrupt races, cache incoherence, and incorrect peripheral access. This skill provides platform-specific design, implementation, and validation guidance.
Supports: Claude Codex Code(CC)
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Copy this request to your Agent. It includes the canonical Skill page and manifest.
Agent request
Review the Skillstore skill "arm-cortex-expert" from https://skillstore.io/skills/sickn33-arm-cortex-expert.md and its manifest at https://skillstore.io/api/skills/sickn33-arm-cortex-expert/manifest. Verify the artifact. You may proceed after verification, subject to the environment's own policy.Your Agent should still show its plan and request any confirmation required by the security policy.
Agent-readable resources
Use these links when an AI agent, crawler, or script needs clean context instead of reading the full page.
Test it
Using "arm-cortex-expert". Explain why a Cortex-M7 DMA receive buffer contains stale data.
Expected outcome:
- Likely cause: the CPU cache still holds old lines after DMA writes.
- Recommended checks: confirm 32-byte alignment, buffer sizing, memory attributes, and cache invalidation before CPU reads.
- Validation: compare cached and non-cacheable buffer behavior while tracing DMA completion.
Using "arm-cortex-expert". Plan a nonblocking SPI sensor driver for an STM32 board.
Expected outcome:
- Architecture: separate transport, sensor protocol, and application state.
- Flow: start transactions asynchronously, advance state in completion callbacks, and report timeout or bus errors.
- Validation: test identity reads, malformed responses, timeout recovery, concurrent access, and maximum transfer rate.
Using "arm-cortex-expert". Interpret a HardFault with CFSR, BFAR, PC, and LR values.
Expected outcome:
- First classify the fault bits, then verify whether the fault-address register is valid.
- Map the program counter to a symbol and inspect the stacked arguments around the failing instruction.
- Confirm the leading hypothesis with watchpoints, stack usage measurements, and a minimized reproduction.
Security Audit
Safev5 • 7/23/2026 Open versioned report
All 34 static alerts are false positives caused by Markdown backticks, code fences, a Rust API named with, and legitimate firmware diagnostics. The skill contains no executable scripts, command execution, reconnaissance intent, prompt injection, or data-exfiltration behavior.
1
Files scanned
308
Lines analyzed
0
Review items
0
False positives ignored
Risk Factors
⚡ Contains scripts (1)
⚙️ External commands (31)
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No confirmed security findings were detected by the latest completed static and semantic audit. This does not prove the skill has no side effects.
Audited by: codex View Audit History →
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APA citation
sickn33. (2026). arm-cortex-expert security audit report (audit version 5) [Author version unspecified]. Skillstore. https://skillstore.io/skills/sickn33-arm-cortex-expert/audits/5BibTeX citation
@techreport{sickn33-sickn33-arm-cortex-expert-2026,
author = {sickn33},
title = {arm-cortex-expert security audit report (audit version 5)},
institution = {Skillstore},
year = {2026},
number = {5},
url = {https://skillstore.io/skills/sickn33-arm-cortex-expert/audits/5},
note = {Author version unspecified}
}CITATION.cff
cff-version: 1.2.0
message: "If you use this Skill, cite its author and this versioned security audit report."
title: "arm-cortex-expert security audit report (audit version 5)"
version: "unspecified"
type: report
authors:
- name: "sickn33"
date-released: "2026-07-23"
url: "https://skillstore.io/skills/sickn33-arm-cortex-expert/audits/5"
identifiers:
- type: other
value: "skillstore:sickn33-arm-cortex-expert:audit:5"
description: "Skillstore immutable audit report identifier"
Skillstore Score
Why this score Evidence Confidence: High 55
Architecture
85
Maintainability
87
Content
69
Community
83
Spec Compliance
What You Can Build
Develop a Peripheral Driver
Create a nonblocking driver design with initialization, transactions, interrupt handling, error recovery, and target validation.
Review Real-Time Behavior
Assess interrupt priorities, critical sections, DMA coherency, memory barriers, and latency risks before integration.
Diagnose Target Faults
Interpret fault registers, stack frames, memory access failures, and platform constraints to plan focused experiments.
Try These Prompts
Explain Interrupt Priorities
Explain the Cortex-M interrupt priority model for [MCU] and recommend priorities for [peripherals]. Include assumptions, tradeoffs, and verification steps.
Design an SPI Driver
Design a nonblocking SPI sensor driver for [board] using [framework]. Cover initialization, transactions, error handling, interrupts, and a target test plan.
Review DMA Safety
Review this [language] DMA implementation for [MCU]. Identify alignment, cache coherency, synchronization, memory barrier, and lifetime defects, then propose corrected architecture.
Analyze a HardFault
Analyze the supplied HardFault registers and stack frame for [MCU]. Rank likely causes, map evidence to each cause, and define confirming experiments.
Best Practices
- Provide the exact MCU, board revision, framework, compiler, clock configuration, and peripheral requirements.
- Check generated advice against the reference manual, datasheet, errata, and platform library version.
- Validate on target hardware with fault injection, timing measurements, boundary cases, and recovery tests.
Avoid
- Do not apply Cortex-M7 cache guidance to devices without caches or identical memory architecture.
- Do not copy register addresses, interrupt priorities, or DMA mappings between MCU families.
- Do not accept generated firmware without compilation, static analysis, hardware tests, and electrical constraint review.
Frequently Asked Questions
Which platforms does this skill cover?
It covers Teensy 4.x, STM32 F4, F7, and H7, nRF52, and SAMD Cortex-M platforms.
Which programming languages can it support?
It provides guidance for C, C++, and Rust embedded development, depending on the selected platform and framework.
Can it generate complete drivers?
It can propose complete driver modules, but you must compile, review, and test them against your exact hardware.
Does it replace the MCU reference manual?
No. Use the current reference manual, datasheet, errata, and framework documentation as authoritative sources.
Can it debug hardware remotely?
It can analyze supplied logs, fault registers, traces, and code, but it cannot observe or measure the physical target.
What information should I provide?
Provide the MCU, board, toolchain, framework, clock tree, pin mapping, peripheral requirements, failure evidence, and expected behavior.